National Repository of Grey Literature 16 records found  1 - 10next  jump to record: Search took 0.01 seconds. 
Concept of Fast Charging Station with Accumulation for Electric Vehicles
Miškovský, Ján ; Morávek, Jan (referee) ; Mastný, Petr (advisor)
Main purpose of the thesis is the creation of a concept a fast-charging station associated with accumulation that uses renewable source. The introduction of the thesis describes a standard that specifies the charge of electric vehicles using direct and alternating current as well. It depicts an overview of using charging connectors. The first part also deals with overview of the technology of renewable sources and exploitation energy storage system for charging station. The second part introduces the theoretical basement for mathematical model of the charging station in Matlab/Simulink. The function of model station is verified by a physical laboratory model. For options verification of the connection station to the distribution net is created simulation of voltage losses in Matlab/Simulink. The thesis shows four 24 hours’ scenarios that have been simulated. According to the assumptions of simulation, the technology of station and connecting component is suggested. Next is the designed energy and financial analysis of the project charging station until 2030.
Model of Tasks with Constrains and Mechanisms of Their Scheduling in UPPAAL SMC
Palúch, Filip ; Podivínský, Jakub (referee) ; Strnadel, Josef (advisor)
The effort of this thesis is the review of mechanisms of tasks planning in singlecore environment. Each models are designed and implemented in tool UPPAAL using these mechanisms. The main focus in this thesis is the tool UPPAAL. Result of this thesis is verification of each mechanisms properties received from implementation of models in UPPAAL. TimesTool and Cheddar are the tools which are used for comparing our results from UPPAAL.
Network Configuration Synthesis and Verification
Černeková, Alžbeta ; Veselý, Vladimír (referee) ; Ryšavý, Ondřej (advisor)
The subject of this master's thesis is to address the topic of network devices configuring. It resolves the problems related to simplifying certain parts of configuration while eliminating frequent errors or issues. It introduces a solution to setting of IP addresses on router's interfaces. Furthermore it presents the generation of configuration for particular dynamic routing scenarios and its application and methods for its verification on network devices. It also demonstrates the preparation of configuration of VPN tunnel between two devices. The conclusion of this thesis contains possibilities for further extensions or improvements.
Acquisition and Recognition of 3D Signature
Molitoris, Miloš ; Dvořák, Michal (referee) ; Drahanský, Martin (advisor)
This work deals with methods of signing in 3D space, selecting a suitable scan model, obtaining a sufficient number of samples to create a database, and finally verifying signatures. The first part deals with the issue of existing solutions and methods of signature verification, further image processing required for marker shooting in 3D space. The following sections are dedicated to design a unique signature solution in free space using a pen without any contact. Two shooting models have been designed using cameras or Leap Motion sensor. The application was implemented based on DTW algorithm using this sensor resulting in a dynamic signature verification system. Furthermore, the work includes a description using of database creation and experimental signature verification. At the end, we find an assessment of the security and error rate of the system that is compared to other methods. The result of this thesis is an application for 3D signature capture and recognition with the potential of a new technique for secure signature.
Automation of Verification Using Artificial Neural Networks
Fajčík, Martin ; Husár, Adam (referee) ; Zachariášová, Marcela (advisor)
The goal of this thesis is to analyze and to find solutions of optimization problems derived from automation of functional verification of hardware using artificial neural networks. Verification of any integrated circuit (so called Design Under Verification, DUV) using technique called coverage-driven verification and universal verification methodology (UVM) is carried out by sending stimuli inputs into DUV. The verification environment continuously monitors percentual coverage of DUV functionality given by the specification. In current context, coverage stands for measurable property of DUV, like count of verified arithemtic operations or count of executed lines of code. Based on the final coverage, it is possible to determine whether the coverage of DUV is high enough to declare DUV as verified. Otherwise, the input stimuli set needs to change in order to achieve higher coverage. Current trend is to generate this set by technique called constrained-random stimulus generation. We will practice this technique by using pseudorandom program generator (PNG). In this paper, we propose multiple solutions for following two optimization problems. First problem is ongoing modification of PNG constraints in such a way that the DUV can be verified by generated stimuli as quickly as possible. Second one is the problem of seeking the smallest set of stimuli such that this set verifies DUV. The qualities of the proposed solutions are verified on 32-bit application-specific instruction set processors (ASIPs) called Codasip uRISC and Codix Cobalt.
Compiler of C Language Fragment to ARTMC Tool
Marušák, Matej ; Hruška, Martin (referee) ; Rogalewicz, Adam (advisor)
Abstract With growing complexity of software programs the need for automated analysis and verifi- cation grows as well. Reasearch group VeriFIT based on Faculty of Information Technology of Brno University of Technology is involved in research of this area. One of the developed tools is the ARTMC tool. This bachelor’s thesis designs and implements compiler of C lan- guage fragment into input format of the ARTMC tool. Implemented compiler makes work with ARTMC tool much easier, since the input format is not suitable for manual creation.
Comparison of the determination of hormones (Follicle stimulating hormone, Luteinizing hormone, Prolactin, Testosterone, Progesteron) by two analytical systems. Converting accredited method and its verification.
Kucejová, Soňa ; Martínková, Markéta (advisor) ; Mrízová, Iveta (referee)
Analytical system ARCHITECT i2000SR was verified according to requirements of ÚLBLD VFN and 1. LF UK laboratory in Prague. Repeatability, intermediate precision, and measurement uncertainty were determined as performance parameters for verification of analytical assays for testosterone, progesterone, luteinizing hormone, follicule stimulating hormone and prolactin. Results of Lyphochek control samples, which were measured, were consistent with values given by manufacture. Repeatability: coefficients of variation for testosterone Lyphochek 1 6,81%, for Lyphochek 3 6,40%, progesterone 2,4% and 1,8%, luteinizing hormone 5,38% and 1,89%, follicle stimulating hormone 5,12% and 3,24% prolactin 1,45% a 1,83%. Intermediate precision: coefficients of variation for testosterone Lyphochek 1 6,02%, Lyphochek 2 3,60%, Lyphochek 3 3,07%, progesterone 7,9%, 4,9% and 5,8%, luteinizing hormone 4,50%, 5,51% and 5,83%, follicle stimulating hormone 4,00%, 3,72% and 4,87%, prolactin 4,60%, 4,20% and 5,00%. Measurement uncertainty: testosterone 6,02%, progesterone 7,9%, luteinizing hormone 5,83%, follicle stimulating hormone 4,87%, prolactin 5,00%. Analytical System Architect i2000SR was compared with previously used ADVIA Centaur system to find out, whether it is possible to convert the method Centaur Testosterone,...
Visualization and verification of plans
Glinský, Radoslav ; Barták, Roman (advisor) ; Dvořák, Filip (referee)
Title: Visualization and Verification of Plans Author: Radoslav Glinský Department: Department of Theoretical Computer Science and Mathematical Logic Supervisor of the bachelor thesis: Doc. RNDr. Roman Barták, Ph.D. Abstract: Plan analysis is an important part of complete planning systems. In order to make even larger plans transparent and human readable, we have developed a program which helps users with the analysis and visualization of plans. This program is called VisPlan - Interactive Visualization and Verification of Plans. VisPlan is an inevitable part of this thesis as it practically implements its plan verification and visualization solutions. VisPlan finds and displays causal relations between actions, it identifies possible flaws in plans (and thus verifies plans' correctness), it highlights the flaws found in the plan and finally, it allows users to interactively modify the plan and hence manually repair the flaws or just fine-tune the plan. Keywords: Planning, Artificial Intelligence, PDDL, Verification
Acquisition and Recognition of 3D Signature
Molitoris, Miloš ; Dvořák, Michal (referee) ; Drahanský, Martin (advisor)
This work deals with methods of signing in 3D space, selecting a suitable scan model, obtaining a sufficient number of samples to create a database, and finally verifying signatures. The first part deals with the issue of existing solutions and methods of signature verification, further image processing required for marker shooting in 3D space. The following sections are dedicated to design a unique signature solution in free space using a pen without any contact. Two shooting models have been designed using cameras or Leap Motion sensor. The application was implemented based on DTW algorithm using this sensor resulting in a dynamic signature verification system. Furthermore, the work includes a description using of database creation and experimental signature verification. At the end, we find an assessment of the security and error rate of the system that is compared to other methods. The result of this thesis is an application for 3D signature capture and recognition with the potential of a new technique for secure signature.
Compiler of C Language Fragment to ARTMC Tool
Marušák, Matej ; Hruška, Martin (referee) ; Rogalewicz, Adam (advisor)
Abstract With growing complexity of software programs the need for automated analysis and verifi- cation grows as well. Reasearch group VeriFIT based on Faculty of Information Technology of Brno University of Technology is involved in research of this area. One of the developed tools is the ARTMC tool. This bachelor’s thesis designs and implements compiler of C lan- guage fragment into input format of the ARTMC tool. Implemented compiler makes work with ARTMC tool much easier, since the input format is not suitable for manual creation.

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